Local Microcode Compaction Techniques
ACM Computing Surveys (CSUR)
Computer Logic, Testing and Verification
Computer Logic, Testing and Verification
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Introduction to Switching Theory and Logical Design
Introduction to Switching Theory and Logical Design
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '78 Proceedings of the 15th Design Automation Conference
Test generation for programmable logic arrays
DAC '82 Proceedings of the 19th Design Automation Conference
A New Approach to the Design of Testable PLA's
IEEE Transactions on Computers
The Complexity of Generating Minimum Test Sets for PLA's and Monotone Combinational Circuits
IEEE Transactions on Computers
A unified treatment of PLA faults by Boolean differences
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Design-for-testability of PLA's using statistical cooling
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Analysis of Testable PLA Designs
IEEE Design & Test
An effective BIST scheme for carry-save and carry-propagate array multipliers
ATS '95 Proceedings of the 4th Asian Test Symposium
The effectiveness of different test sets for PLAs
EURO-DAC '90 Proceedings of the conference on European design automation
Experiments with autonomous test of PLAs
EURO-DAC '91 Proceedings of the conference on European design automation
Online multiple error detection in crossbar nano-architectures
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
An algorithmic branch and bound method for PLA test pattern generation
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Online detection of multiple faults in crossbar nano-architectures using dual rail implementations
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
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PLATypus (PLA Test pattern generation and logic simulation tool) is an efficient tool for large PLAs which is interfaced with other existing PLA tools such as the constrained/unconstrained, simple/multiple folding program PLEASURE and the logic minimizer ESPRESSO II-C developed at the University of California at Berkeley. PLATYPUS uses biased random test generation as a quick preprocess followed by a deterministic test generation process to achieve the best balance between efficient run time and test set minimality. The algorithm adopted in the deterministic phase is exact, i.e., it achieves the highest possible test coverage by generating a test for every testable fault. Powerful heuristics are introduced in the area of fault processing order, backend fault simulation, “don't-care” bit fixing, and on-the-fly test compaction to achieve the best performance of PLATYPUS. The deterministic test generation algorithm is based on both complementation and tautology check of a logic cover. Both complementation and tautology check are performed by an advanced method used in the logic minimizer ESPRESSO-II. PLATYPUS supports both folded and unfolded PLAs, and both crosspoint and stuck-at fault models. PLATYPUS can also be used as a logic simulation tool and redundancy identifier. Test pattern generation has been performed by PLATYPUS on a large number of industrial PLAs.