PLATYPUS: a PLA test pattern generation tool
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Computer Logic, Testing and Verification
Computer Logic, Testing and Verification
DAC '84 Proceedings of the 21st Design Automation Conference
The effectiveness of different test sets for PLAs
EURO-DAC '90 Proceedings of the conference on European design automation
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The calculation of test patterns for PLAs is an expensive and time consuming task if a general purpose test pattern generation program is used. A unified treatment of faults in PLAs and a test pattern generation algorithm based on the calculation of Boolean differences is given in this paper. Calculating the difference between the Boolean functions of the faulty and the fault free circuit guarantees that a test for a given fault is found if it exists. By tailoring the algorithm to the specific structure of programmable logic arrays a powerful tool for the test pattern calculation for PLAs is obtained. An important feature of the method is the ease of incorporating different fault assumptions.