Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Minimization by the D Algorithm
IEEE Transactions on Computers
A Computer Algorithm for Minimizing Reed-Muller Canonical Forms
IEEE Transactions on Computers
On the verification of sequential machines at differing levels of abstraction
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Logic verification algorithms and their parallel implementation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Minimizability of Random Boolean Functions
IEEE Transactions on Computers
New methods in the analysis of logic minimization data and algorithms
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Test pattern generation for sequential MOS circuits by symbolic fault simulation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A methodology for hardware verification based on logic simulation
Journal of the ACM (JACM)
Symbolic simulation—techniques and applications
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Negation Trees: A Unified Approach to Boolean Function Complementation
IEEE Transactions on Computers
A fast algorithm to minimize multi-output mixed-polarity generalized Reed-Muller forms
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Why partial design verification works better than it should
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
PLATYPUS: a PLA test pattern generation tool
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Symbolic manipulation of Boolean functions using a graphical representation
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A unified treatment of PLA faults by Boolean differences
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An Approach for Analysing the Propagation of Data Errors in Software
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A new integrated system for PLA testing and verification
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '81 Proceedings of the 18th Design Automation Conference
Techniques for programmable logic array folding
DAC '82 Proceedings of the 19th Design Automation Conference
Implication algorithms for MOS switch level functional macromodeling implication and testing
DAC '82 Proceedings of the 19th Design Automation Conference
Logical correctness by construction
DAC '82 Proceedings of the 19th Design Automation Conference
Parallel processing, special-purpose hardware, and DA applications
CSC-83 Proceedings of the 1983 computer science conference
EPIC: Profiling the Propagation and Effect of Data Errors in Software
IEEE Transactions on Computers
Test Generation Algorithms for Computer Hardware Description Languages
IEEE Transactions on Computers
Input Variable Assignment and Output Phase Optimization of PLA's
IEEE Transactions on Computers
Redundancy and Don't Cares in Logic Synthesis
IEEE Transactions on Computers
GRIN: interactive graphics for modeling solids
IBM Journal of Research and Development
IBM Journal of Research and Development
Design verification system for large-scale LSI designs
IBM Journal of Research and Development
Exclusive-OR representations of Boolean functions
IBM Journal of Research and Development
Test generation for FET switching circuits
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
VM image update notification mechanism based on pub/sub paradigm in cloud
Proceedings of the 5th Asia-Pacific Symposium on Internetware
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