Computer Logic, Testing and Verification
Computer Logic, Testing and Verification
Test generation for large logic networks
DAC '77 Proceedings of the 14th Design Automation Conference
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As the complexity of VLSI circuits continues to increase, the need to test for failures has become imperative. The problem of generating test to detect failures on FET transistor networks has been unsolved for all but simple cases. In this paper we describe an effective method for computing test for failures for FET switching networks. Here we define a function-preserving, failure-preserving transformation of a switching network into a logic network. There are efficient means for computing tests for failures in logic networks, specifically, the D-algorithm. Tests so computed for the image logic network are automatically tests for failures in the original switching network. In other words the logic network so generated not only computes the same function; it also has the same failure-structure. Tests for the logic-network failures are computed by efficient test-generation procedures, using the D-algorithm (1980). It is proven for the transformation that a test for a stuck failure in the logic network is simultaneously a test for a short (or open) for the corresponding switch in the switching network. Run time for the transformation, from switching to logic network, increases linearly with the complexity of the switching network, so that its run time can be neglected. A program SW2BOOL of the algorithm (written in Pascal) clearly verify the claims as to correctness and speed.