Introduction to an LSI test system
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Automatic checking of logic design structures For compliance with testability ground rules
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
25 years of DAC Papers on Twenty-five years of electronic design automation
PODEM-X: An automatic test generation system for VLSI logic structures
25 years of DAC Papers on Twenty-five years of electronic design automation
Boundary-scan design principles for efficient LSSD ASIC testing
IBM Journal of Research and Development
A Test Methodology for High Performance MCMs
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
Circuit partitioning for efficient logic BIST synthesis
Proceedings of the conference on Design, automation and test in Europe
IBM FSD VLSI chip design methodology
DAC '83 Proceedings of the 20th Design Automation Conference
Test generation for scan design circuits with tri-state modules and bidirectional terminals
DAC '83 Proceedings of the 20th Design Automation Conference
Diagnosis of TCM failures in the IBM 3081 Processor complex
DAC '83 Proceedings of the 20th Design Automation Conference
Chip partitioning aid: A design technique for partitionability and testability in VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
PODEM-X: An automatic test generation system for VLSI logic structures
DAC '81 Proceedings of the 18th Design Automation Conference
Test data verification - not just the final step for test data before release for production testing
DAC '81 Proceedings of the 18th Design Automation Conference
A test methodology for large logic networks
DAC '78 Proceedings of the 15th Design Automation Conference
Selective controllability: A proposal for testing and diagnosis
DAC '78 Proceedings of the 15th Design Automation Conference
A new test pattern generation system
DAC '80 Proceedings of the 17th Design Automation Conference
Introduction to an LSI test system
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Automatic checking of logic design structures For compliance with testability ground rules
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Scan Latch Design for Test Applications
Journal of Electronic Testing: Theory and Applications
AUTOMATIC SYSTEM LEVEL TEST GENERATION AND FAULT LOCATION FOR LARGE DIGITAL SYSTEMS
DAC '78 Proceedings of the 15th Design Automation Conference
Design for Testability A Survey
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
Design automation and the programmable logic array macro
IBM Journal of Research and Development
IBM Journal of Research and Development
Automated diagnostic methodology for the IBM 3081 processor complex
IBM Journal of Research and Development
Design verification system for large-scale LSI designs
IBM Journal of Research and Development
Product quality level monitoring and control for logic chips and modules
IBM Journal of Research and Development
Failure diagnosis on the LT1280
IBM Journal of Research and Development
Test generation for FET switching circuits
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
| Hi-index | 0.01 |
A system for automatic test pattern generation for large logic networks is described. The network to be tested is assumed to comply with a set of ground rules for testability. The system includes features for automatic subdivision of the network into easily tested sub-networks, automatic test generation programs, and a post-processor which produces a highly efficient test program. Applications to fault diagnosis, and to fast processing of design changes and variations for machine features are considered.