Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A logic chip delay-test method based on system timing
IBM Journal of Research and Development
Built-in self-test support in the IBM engineering design system
IBM Journal of Research and Development
Generation of high quality non-robust tests for path delay faults
DAC '94 Proceedings of the 31st annual Design Automation Conference
Trends in Silicon-On-Silicon Multichip Modules
IEEE Design & Test
Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Stuck Fault and Current Testing Comparison Using CMOS Chip Test
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Delay Test: The Next Frontier for LSSD Test Systems
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Test generation for large logic networks
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
Delay fault coverage, test set size, and performance trade-offs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fundamentals of MCM Testing and Design-for-Testability
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
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Satellite and avionics applications represent an ideal application for the tremendous performance, cost, space, andreliability benefits of MCMs. These advantages are only realized,however, if accompanied by an efficient test strategy whichverifies defect-free fabrication. This paper describes a methodology developed to test high performance VLSI CMOS ICs thathave been mounted onto a multi-chip silicon substrate. A teststrategy, which addresses testing from the wafer level through tothe populated substrate, is detailed. This strategy uses acombination of LSSD, AC LSSD-On-Chip Self Test, Deterministic Delay Fault Testing, and Design for Partitionability to ensure high testquality at a reasonable cost. The methodology is then contrastedto alternative approaches.