Introduction to an LSI test system
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Automatic checking of logic design structures For compliance with testability ground rules
DAC '77 Proceedings of the 14th Design Automation Conference
Test generation for large logic networks
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
25 years of DAC Papers on Twenty-five years of electronic design automation
A simplified six-waveform type method for delay fault testing
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A logic chip delay-test method based on system timing
IBM Journal of Research and Development
An efficient delay test generation system for combinational logic circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Automatic incorporation of on-chip testability circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Correlation-reduced scan-path design to improve delay fault coverage
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Delay test effectiveness evaluation of LSSD-based VLSI logic circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The Total Delay Fault Model and Statistical Delay Fault Coverage
IEEE Transactions on Computers
A novel approach to delay-fault diagnosis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A quantitative measure of robustness for delay fault testing
EURO-DAC '92 Proceedings of the conference on European design automation
An efficient path delay fault coverage estimator
DAC '94 Proceedings of the 31st annual Design Automation Conference
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A Test Methodology for High Performance MCMs
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
Quality Determination for Gate Delay Fault Tests Considering Three-State Elements
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
PATEGE: an automatic DC parametric test generation system for series gated ECL circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Analysis of timing failures due to random AC defects in VLSI modules
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A delay test system for high speed logic LSI's
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A Statistical Model for Delay-Fault Testing
IEEE Design & Test
Delay-Fault Diagnosis by Critical-Path Tracing
IEEE Design & Test
Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Introduction to an LSI test system
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Automatic checking of logic design structures For compliance with testability ground rules
DAC '77 Proceedings of the 14th Design Automation Conference
Test generation for large logic networks
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
Multiple-Output Propagation Transition Fault Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Design for Testability in Nanometer Technologies; Searching for Quality
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
On the fault coverage of delay fault detecting tests
EURO-DAC '90 Proceedings of the conference on European design automation
Design for Testability A Survey
IEEE Transactions on Computers
An Experimental Delay Test Generator for LSI Logic
IEEE Transactions on Computers
Testability features of the MC68060 microprocessor
ITC'94 Proceedings of the 1994 international conference on Test
Statistical delay fault coverage and defect level for delay faults
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
On the detection of delay faults
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Delay test generation 1: concepts and coverage metrics
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Delay test generation 2: algebra and algorithms
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
LSI logic testing: an overview
IEEE Transactions on Computers
Automatic test pattern generation
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
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Conflicting needs complicate the task of testing LSI chips. As system designs come to require better and more predictable performance, it becomes increasingly difficult to develop tests for application at the product I/O pins to verify that each internal device has been manufactured correctly. Any of numerous kinds of random manufacturing defect, though allowing correct dc operation, can cause a device to perform at a speed below that specified for it. This type of defect has led to the development of several testing methods that have become conventional. For numerous reasons, however, the conventional methods cannot be extended to LSI without certain design constraints. For the LSSD—level-sensitive scan design—constraints, dc fault-oriented testing has been extended to delay faults. The strategy is to delay-test each block input and/or output in both its longest and its shortest sensitizable delay paths. An algorithm for automatic generation of such delay tests has been developed, and extended to generate delay tests for designer-specified critical paths.