Analysis of timing failures due to random AC defects in VLSI modules
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Statistical techniques of timing verification
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
An efficient delay test generation system for combinational logic circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
On testing wave pipelined circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Quality Determination for Gate Delay Fault Tests Considering Three-State Elements
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit?
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Identification of delay measurable PDFs using linear dependency relationships
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The authors propose a statistical model for measuring delay-fault coverage. The model provides a figure of merit for delay testing in the same way that fault coverage provides one for the testing of single stuck-at faults. The mode measures test effectiveness in terms of the propagation delay of the path to be tested, the size of the delay defect, and the system clock interval, and then combines the data for all delay faults to measure total delay-fault coverage. The authors also propose a model for measuring the defect level as a function of the manufacturing yield and the predictions of the statistical delay-fault coverage model.