Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Statistical failure analysis of system timing
IBM Journal of Research and Development
Clocking Schemes for High-Speed Digital Systems
IEEE Transactions on Computers
The Total Delay Fault Model and Statistical Delay Fault Coverage
IEEE Transactions on Computers
IBM Enterprise System/9000 clock system: a technology and system perspective
IBM Journal of Research and Development
SCAT—a new statistical timing verifier in a silicon compiler system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Plug-in timing models for an abstract timing verifier
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A Statistical Model for Delay-Fault Testing
IEEE Design & Test
The CRITTER system: Automated critiquing of digital circuit designs
DAC '84 Proceedings of the 21st Design Automation Conference
Statistical delay fault coverage and defect level for delay faults
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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Timing verification of VLSI designs using statistical techniques such as those implemented in Hitchcock's Timing Analysis1 permit a far more precise assessment of machine performance than previous techniques. The accuracy of these results is affected by proper user specification of statistical input parameters and by the algorithmic treatment of the system design. Since these items are both system and technology dependent, the system designer must understand them and apply appropriate statistical techniques in order to insure a properly verified design. This paper both outlines the mathematical derivations and illustrates the magnitude of the improvements to be obtained.