An efficient delay test generation system for combinational logic circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Analysis of timing failures due to random AC defects in VLSI modules
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Quality level and fault coverage for multichip modules
DAC '83 Proceedings of the 20th Design Automation Conference
Statistical techniques of timing verification
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
Delay Fault Coverage Enhancement Using Variable Observation Times
Journal of Electronic Testing: Theory and Applications
Reduction of Number of Paths to be Tested in Delay Testing
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Identification of robust untestable path delay faults
ATS '95 Proceedings of the 4th Asian Test Symposium
Delay Fault Coverage Enhancement Using Multiple Test Observation Times
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A realistic timing test model and its applications in high-speed interconnect devices
Journal of Electronic Testing: Theory and Applications
| Hi-index | 14.98 |
Delay testing at the operational system clock rate can detect system timing failures caused by delay faults. However, delay fault coverage in terms of the percentage of the number of tested faults may not be an effective measure of delay testing. A quantitative delay fault coverage model to provide a figure of merit for delay testing is presented. System sensitivity of a path to a delay fault along that path and the effectiveness of a delay test are described in terms of the propagation delay of the path under test and the delay defect size. A new statistical delay fault coverage model is established. A defect level model is also proposed as a function of the yield of a manufacturing process and the new statistical delay fault coverage. A new delay testing strategy driven by the defect level for delay faults is proposed.