A realistic timing test model and its applications in high-speed interconnect devices

Authors:
Baosheng Wang;Andy Kuo;Touraj Farahmand;André Ivanov;Yong B. Cho;Sassan Tabatabaei
Affiliations:
SoC Laboratory, University of British Columbia, Canada;SoC Laboratory, University of British Columbia, Canada;SoC Laboratory, University of British Columbia, Canada;SoC Laboratory, University of British Columbia, Canada;Department of Electronics Engineering, Konkuk University, Seoul, Korea;Guide Technology Inc., Sunnyvale, California
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2005

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Abstract

This paper extends the timing test model in [5] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures' impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, Parallel/Serial RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a test escape of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter.