Timing Yield Calculation Using an Impulse-train Approach

Authors:
Srinath R. Naidu
Affiliations:
Department of Electrical Engineering, Eindhoven University of Technology, The Netherlands
Venue:
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Year:
2002

Citing 2
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Abstract

This paper presents a new method to compute the probability distribution of the delay of a combinational circuit and uses it to obtain an estimate of the yield of the process that manufactures the circuit. We assume a simple delay model assigning a triangular distribution to the delay of a gate and ignore the logical function of the gate and the pin-to-pin delay. The method can handle tree-like circuits as well as circuits with reconvergent fanout in them. The chief advantage of this method over conventional Monte-Carlo simulation is that it is much faster while providing comparable quality.