A performance optimization method by gate sizing using statistical static timing analysis
ISPD '00 Proceedings of the 2000 international symposium on Physical design
A statistical static timing analysis considering correlations between delays
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Statistical timing analysis using bounds and selective enumeration
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Statistical timing analysis using bounds and selective enumeration
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Timing Yield Calculation Using an Impulse-train Approach
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A methodology to improve timing yield in the presence of process variations
Proceedings of the 41st annual Design Automation Conference
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
Proceedings of the 41st annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Toward stochastic design for digital circuits: statistical static timing analysis
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Statistical Timing Analysis Using Bounds
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Modeling multiple input switching of CMOS gates in DSM technology using HDMR
Proceedings of the conference on Design, automation and test in Europe: Proceedings
NBTI-aware circuit node criticality computation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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In this paper a new problem definition of statistical timing analysis is formulated. Two efficient methods that consider only dominant long paths are employed to approach this problem. The influence of the correlation of node delays on the probability distribution of the longest path delay is studied in details. The experimental results show that the probability distribution of the longest path delay is greatly influenced by the correlation of nodes and by the presence of many dominant long paths. The results also show that the probability distribution obtained by our approaches is well tracked to the distribution obtained by the whole circuit simulation with much less computation time.