Block-based Static Timing Analysis with Uncertainty

Authors:
Anirudh Devgan;Chandramouli Kashyap
Affiliations:
IBM Research, Austin, TX;IBM Microelectronics, Austin, TX
Venue:
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Year:
2003

Citing 11
Cited 80

Fast statistical timing analysis by probabilistic event propagation

Proceedings of the 38th annual Design Automation Conference
Uncertainty-aware circuit optimization

Proceedings of the 39th annual Design Automation Conference
A general probabilistic framework for worst case timing analysis

Proceedings of the 39th annual Design Automation Conference
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

Proceedings of the 39th annual Design Automation Conference
Statistical timing analysis using bounds and selective enumeration

Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Statistical Timing Analysis of Combinational Circuits

ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Statistical timing for parametric yield prediction of digital integrated circuits

Proceedings of the 40th annual Design Automation Conference
Timing analysis for nMOS VLSI

DAC '83 Proceedings of the 20th Design Automation Conference
Timing Verification and the Timing Analysis program

DAC '82 Proceedings of the 19th Design Automation Conference
A New Statistical Approach to Timing Analysis of VLSI Circuits

VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Timing Yield Estimation from Static Timing Analysis

ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design

Fast statistical timing analysis handling arbitrary delay correlations

Proceedings of the 41st annual Design Automation Conference
STAC: statistical timing analysis with correlation

Proceedings of the 41st annual Design Automation Conference
Statistical timing analysis based on a timing yield model

Proceedings of the 41st annual Design Automation Conference
On path-based learning and its applications in delay test and diagnosis

Proceedings of the 41st annual Design Automation Conference
Statistical gate delay model considering multiple input switching

Proceedings of the 41st annual Design Automation Conference
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining

Proceedings of the 41st annual Design Automation Conference
Statistical Timing Based Optimization using Gate Sizing

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Statistical Timing Analysis using Levelized Covariance Propagation

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation

Proceedings of the 2005 international symposium on Physical design
Fast interval-valued statistical interconnect modeling and reduction

Proceedings of the 2005 international symposium on Physical design
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions

Proceedings of the 42nd annual Design Automation Conference
Correlation-aware statistical timing analysis with non-gaussian delay distributions

Proceedings of the 42nd annual Design Automation Conference
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model

Proceedings of the 42nd annual Design Automation Conference
Circuit optimization using statistical static timing analysis

Proceedings of the 42nd annual Design Automation Conference
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance

Proceedings of the 42nd annual Design Automation Conference
Statistical static timing analysis: how simple can we get?

Proceedings of the 42nd annual Design Automation Conference
Variability inspired implementation selection problem

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Interval-valued reduced order statistical interconnect modeling

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Static statistical timing analysis for latch-based pipeline designs

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient statistical timing analysis through error budgeting

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Clock schedule verification under process variations

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A path-based methodology for post-silicon timing validation

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA)

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An exact algorithm for the statistical shortest path problem

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Block based statistical timing analysis with extended canonical timing model

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Advances in Computation of the Maximum of a Set of Random Variables

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Statistical Analysis of Capacitance Coupling Effects on Delay and Noise

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Application of fast SOCP based statistical sizing in the microprocessor design flow

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Statistical timing analysis with two-sided constraints

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A unified framework for statistical timing analysis with coupling and multiple input switching

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis with path reconvergence and spatial correlations

Proceedings of the conference on Design, automation and test in Europe: Proceedings
A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits

Proceedings of the conference on Design, automation and test in Europe: Proceedings
Statistical timing analysis with correlated non-gaussian parameters using independent component analysis

Proceedings of the 43rd annual Design Automation Conference
Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Analysis and modeling of CD variation for statistical static timing

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
An accurate sparse matrix based framework for statistical static timing analysis

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A new statistical max operation for propagating skewness in statistical timing analysis

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Interactive presentation: System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs

Proceedings of the conference on Design, automation and test in Europe
A novel criticality computation method in statistical timing analysis

Proceedings of the conference on Design, automation and test in Europe
Fast second-order statistical static timing analysis using parameter dimension reduction

Proceedings of the 44th annual Design Automation Conference
Statistical performance modeling and optimization

Foundations and Trends in Electronic Design Automation
Variations, margins, and statistics

Proceedings of the 2008 international symposium on Physical design
Non-Gaussian statistical timing models of die-to-die and within-die parameter variations for full chip analysis

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization

Integration, the VLSI Journal
System-level throughput analysis for process variation aware multiple voltage-frequency island designs

ACM Transactions on Design Automation of Electronic Systems (TODAES)
FPCNA: a field programmable carbon nanotube array

Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Process variability-aware transient fault modeling and analysis

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Timing variation-aware task scheduling and binding for MPSoC

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Accelerating statistical static timing analysis using graphics processing units

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Synthesizing a representative critical path for post-silicon delay prediction

Proceedings of the 2009 international symposium on Physical design
A fuzzy optimization approach for variation aware power minimization during gate sizing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical static timing analysis: A survey

Integration, the VLSI Journal
Priority-based routing resource assignment considering crosstalk

Journal of Computer Science and Technology
Statistical timing and leakage power analysis of PD-SOI digital circuits

Analog Integrated Circuits and Signal Processing
Variation estimation and compensation technique in scaled LTPS TFT circuits for low-power low-cost applications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An on-the-fly parameter dimension reduction approach to fast second-order statistical static timing analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A framework for scalable postsilicon statistical delay prediction under process variations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A hierarchy of subgraphs underlying a timing graph and its use in capturing topological correlation in SSTA

Proceedings of the 2009 International Conference on Computer-Aided Design
Design and evaluation of a carbon nanotube-based programmable architecture

International Journal of Parallel Programming
Capturing post-silicon variations using a representative critical path

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accurate estimation of vector dependent leakage power in the presence of process variations

ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Process-induced skew variation for scaled 2-D and 3-D ICs

Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Accurate and analytical statistical spatial correlation modeling based on singular value decomposition for VLSI DFM applications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing modeling for digital sub-threshold circuits

Proceedings of the Conference on Design, Automation and Test in Europe
iRetILP: an efficient incremental algorithm for min-period retiming under general delay model

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Statistical timing yield optimization by gate sizing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing variation-aware scheduling and resource binding in high-level synthesis

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power grid analysis and verification considering temperature variations

Microelectronics Journal
Dynamic clock stretching for variation compensation in VLSI circuit design

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Effect of process variations in 3D global clock distribution networks

ACM Journal on Emerging Technologies in Computing Systems (JETC)
An accurate sparse-matrix based framework for statistical static timing analysis

Integration, the VLSI Journal
Timing yield analysis considering process-induced temperature and supply voltage variations

Microelectronics Journal
Speeding up computation of the max/min of a set of gaussians for statistical timing analysis and optimization

Proceedings of the 50th Annual Design Automation Conference
Hardware/software approaches for reducing the process variation impact on instruction fetches

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Power yield analysis under process and temperature variations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Static timing analysis is a critical step in design of any digitalintegrated circuit. Technology and design trends have ledto significant increase in environmental and process variationswhich need to be incorporated in static timing analysis.This paper presents a new, efficient and accurate block-basedstatic timing analysis technique considering uncertainty.This new method is more efficient as its modelsarrival times as cumulative density functions (CDFs) anddelays as probability functions (PDFs). Computationallysimple expression are presented for basic static timing operations.The techniques are valid for any form of the probabilitydistribution, though the use piecewise linear modelingof CDFs is highlighted in this paper. Reconvergent fanoutsare handled using a new technique that avoids path tracing.Variable accuracy timing analysis can be performed byvarying the modeling accuracy of the piecewise linearmodel. Regular and statistical timing on different parts ofthe circuit can be incorporated into a single timing analysisrun. Accuracy and efficiency of the proposed method is demonstratedfor various ISCAS benchmark circuits.