Performance-impact limited area fill synthesis
Proceedings of the 40th annual Design Automation Conference
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
Computation and Refinement of Statistical Bounds on Circuit Delay
Proceedings of the 40th annual Design Automation Conference
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th annual Design Automation Conference
Toward a systematic-variation aware timing methodology
Proceedings of the 41st annual Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
A Probabilistic Approach to Buffer Insertion
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Manufacturing-Aware Physical Design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
CMOS VLSI Design: A Circuits and Systems Perspective
CMOS VLSI Design: A Circuits and Systems Perspective
RC delay metrics for performance optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect sizing and spacing with consideration of coupling capacitance
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A simple metric for slew rate of RC circuits based on two circuit moments
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variability-Driven Buffer Insertion Considering Correlations
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Fast buffer insertion considering process variations
Proceedings of the 2006 international symposium on Physical design
Dummy fill aware buffer insertion during routing
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Fast min-cost buffer insertion under process variations
Proceedings of the 44th annual Design Automation Conference
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This paper studies the impacts of Chemical Mechanical Polishing (CMP)-induced systematic variation and random channel length (Leff) variation of transistors on interconnect design. We first construct a table look-up based interconnect RC parasitic model considering CMP effects with optimized fill insertion. Based on the model, we solve the simultaneous buffer insertion, wire sizing and fill insertion (SBWF) problem under CMP variation. We also extend the SBWF problem to consider the random Leff variation (SBWF). We approach the resulting vSBWF problem by (1) incorporating probability density function (PDF) into the SBWF algorithm; and (2) developing an efficient heuristic for PDF pruning, whose practical optimality is verified by an accurate but much slower pruning. Experimental results show that the SBWF design improves timing by 1.0% and reduces power by 5.7% on average with 7.4% less buffer area over the conventional buffer insertion and wire sizing design followed by fill insertion (SBWF), and that the vSBWF design reduces yield loss due to CMP and Leff variations by 44.3% on average over the SBWF design. The runtime of vSBWF is 8.3x that of SBWF, and vSBWF for the largest example containing 3103 sinks finishes in 124 minutes.