Proceedings of the 2005 international symposium on Physical design
A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Measuring the gap between FPGAs and ASICs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Logic SER Reduction through Flipflop Redesign
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Implementing DSP Algorithms with On-Chip Networks
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A New Cost-Effective Technique for QoS Support in Clusters
IEEE Transactions on Parallel and Distributed Systems
Testable designs of multiple precharged domino circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power leading-zero counting and anticipation logic for high-speed floating point units
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Tradeoffs in designing accelerator architectures for visual computing
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Accurate linear model for SET critical charge estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffers
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Worst-case performance prediction under supply voltage and temperature variation
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical leakage estimation based on sequential addition of cell leakage currents
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Intel LVS logic as a combinational logic paradigm in CNT technology
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Analog circuit shielding routing algorithm based on net classification
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Wideband ring VCO for cognitive radio five-port receiver
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Control network generator for latency insensitive designs
Proceedings of the Conference on Design, Automation and Test in Europe
Novel library of logic gates with ambipolar CNTFETs: opportunities for multi-level logic synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Statistical time borrowing for pulsed-latch circuit designs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A new DAC mismatch shaping technique for sigma-delta modulators
IEEE Transactions on Circuits and Systems II: Express Briefs
High rate data synchronization in GALS socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of MRAM based logic circuits and its applications
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Physically unclonable functions: manufacturing variability as an unclonable device identifier
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
A case for NEMS-based functional-unit power gating of low-power embedded microprocessors
Proceedings of the 48th Design Automation Conference
An on-chip all-digital PV-monitoring architecture for digital IPs
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
From Transistors to NEMS: Highly Efficient Power-Gating of CMOS Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Parameter variation effects on timing characteristics of high performance clocked registers
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
The complexity of VLSI power-delay optimization by interconnect resizing
Journal of Combinatorial Optimization
Microprocessors & Microsystems
Resilient and adaptive performance logic
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Simple photonic emission analysis of AES: photonic side channel analysis for the rest of us
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
Low-power tri-state buffer in MOS current mode logic
Analog Integrated Circuits and Signal Processing
Thermal stress aware 3D-IC statistical static timing analysis
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Dual-addressing memory architecture for two-dimensional memory access patterns
Proceedings of the Conference on Design, Automation and Test in Europe
Role of power grid in side channel attack and power-grid-aware secure design
Proceedings of the 50th Annual Design Automation Conference
Reliability challenges for electric vehicles: from devices to architecture and systems software
Proceedings of the 50th Annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nano-electro-mechanical relays for FPGA routing: experimental demonstration and a design technique
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Efficient statistical leakage analysis using deterministic cell leakage models
Microelectronics Journal
Leakage energy estimates for HPC applications
E2SC '13 Proceedings of the 1st International Workshop on Energy Efficient Supercomputing
An asymmetric dual-processor architecture for low-power information appliances
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the International Conference on Computer-Aided Design
Temperature tracking: an innovative run-time approach for hardware Trojan detection
Proceedings of the International Conference on Computer-Aided Design
Exploiting replication to improve performances of NUCA-based CMP systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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For both introductory and advanced courses in VLSI design, this authoritative, comprehensive textbook is highly accessible to beginners, yet offers unparalleled breadth and depth for more experienced readers. The Fourth Edition of CMOS VLSI Design: A Circuits and Systems perspective presents broad and in-depth coverage of the entire field of modern CMOS VLSI Design. The authors draw upon extensive industry and classroom experience to introduce todays most advanced and effective chip design practices. They present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples. This book contains unsurpassed circuit-level coverage, as well as a rich set of problems and worked examples that provide deep practical insight to readers at all levels.