Low-power leading-zero counting and anticipation logic for high-speed floating point units

Authors:
Giorgos Dimitrakopoulos;Kostas Galanopoulos;Christos Mavrokefalidis;Dimitris Nikolos
Affiliations:
Technology and Computer Architecture Laboratory, Computer Engineering and Informatics Department, University of Patras, Patras, Greece;Technology and Computer Architecture Laboratory, Computer Engineering and Informatics Department, University of Patras, Patras, Greece;Technology and Computer Architecture Laboratory, Computer Engineering and Informatics Department, University of Patras, Patras, Greece;Technology and Computer Architecture Laboratory, Computer Engineering and Informatics Department, University of Patras, Patras, Greece
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2008

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Abstract

In this paper, a new leading-zero counter (or detector) is presented. New boolean relations for the bits of the leading-zero count are derived that allow their computation to be performed using standard carry-lookahead techniques. Using the proposed approach various design choices can be explored and different circuit topologies can be derived for the design of the leading-zero counting unit. The new circuits can be efficiently implemented either in static or in dynamic logic and require significantly less energy per operation compared to the already known architectures. The integration of the proposed leading-zero counter with the leading-zero anticipation logic is analyzed and the most efficient combination is identified. Finally, a simple yet efficient technique for handling the error of the leading-zero anticipation logic is also presented. The energy-delay behavior of the proposed circuits has been investigated using static and dynamic CMOS implementations in a 130-nm CMOS technology.