Implementation of the Exponential Function in a Floating-Point Unit
Journal of VLSI Signal Processing Systems
Montgomery's Multiplication Technique: How to Make It Smaller and Faster
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Data Integrity in Hardware for Modular Arithmetic
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
The IBM eServer z990 floating-point unit
IBM Journal of Research and Development
Low-power leading-zero counting and anticipation logic for high-speed floating point units
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hybrid LZA: a near optimal implementation of the leading zero anticipator
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Parallel error detection for leading zero anticipation
Journal of Computer Science and Technology
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The floating-point unit of a S/390 CMOS microprocessor is described. It contains a 116 bit fraction dataflow for addition and subtraction and a 64 bit-wide multiplier. Besides the register array, there are no other dataflow macros used; it is fully designed with standard cell books and is placed flat with a timing driven placement algorithm. This design method allows more 'irregular' structures than usually found in custom designs.An overview of the floating-point unit is given and some interesting design items are shown: a 120 bit-wide true-complement adder with precounting of leading zero digits, a signed multiplier with bit-optimized Wallace tree, intensive forwarding in source equal target cases and the checking method.