Floating-Point Unit in Standard Cell Design with 116 Bit Wide Dataflow
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Leading Zero Anticipation and Detection A Comparison of Methods
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Leading One Detection --- Implementation, Generalization, and Application
Leading One Detection --- Implementation, Generalization, and Application
Ultra-low-power adder stage design for exascale floating point units
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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The Leading Zero Anticipator (LZA) is one of the main components used in floating point addition. It tends to be on the critical path, so it has attracted the attention of many researchers in the past. Most LZAs used today can be classified in two categories: exact and inexact. Inexact LZAs are normally preferred due to their shorter critical paths and reduced complexity; however, the inexact LZA requires an additional correct stage. In this paper we present a new LZA architecture that combines ideas taken from prior exact and inexact LZAs. Our new LZA improves the delay of floating point addition by 7--10% compared to state of art techniques as well as reduces hardware area in most cases. We also establish theoretical lower bounds on the delay of an LZA and we show that our LZA is very close to these bounds.