Area-time optimal VLSI integer multiplier with minimum computation time
Information and Control
A course in number theory and cryptography
A course in number theory and cryptography
Hardware Implementation of Montgomery's Modular Multiplication Algorithm
IEEE Transactions on Computers
Space/Time Trade-Offs for Higher Radix Modular Multiplication Using Repeated Addition
IEEE Transactions on Computers
The Area-Time Complexity of Binary Multiplication
Journal of the ACM (JACM)
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
Systolic Modular Multiplication
IEEE Transactions on Computers
A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms
IEEE Transactions on Computers
Exponentiation Using Division Chains
IEEE Transactions on Computers
Area-Time Optimal VLSI Networks for Computing Integer Multiplications and Discrete Fourier Transform
Proceedings of the 8th Colloquium on Automata, Languages and Programming
Faster Modular Multiplication by Operand Scaling
CRYPTO '91 Proceedings of the 11th Annual International Cryptology Conference on Advances in Cryptology
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
CRYPTO '96 Proceedings of the 16th Annual International Cryptology Conference on Advances in Cryptology
The SNAP Project: Design of Floating Point Arithmetic Units
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
Moduli for Testing Implementations of the RSA Cryptosystem
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Montgomery Modular Exponentiation on Reconfigurable Hardware
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Floating-Point Unit in Standard Cell Design with 116 Bit Wide Dataflow
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
On the importance of checking cryptographic protocols for faults
EUROCRYPT'97 Proceedings of the 16th annual international conference on Theory and application of cryptographic techniques
Distinguishing Exponent Digits by Observing Modular Subtractions
CT-RSA 2001 Proceedings of the 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA
Montgomery Exponentiation with no Final Subtractions: Improved Results
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Hardware architectures for public key cryptography
Integration, the VLSI Journal
Accelerating the secure remote password protocol using reconfigurable hardware
Proceedings of the 1st conference on Computing frontiers
Parallel Cryptographic Arithmetic Using a Redundant Montgomery Representation
IEEE Transactions on Computers
Efficient pipelining for modular multiplication architectures in prime fields
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Differential fault analysis on the ARIA algorithm
Information Sciences: an International Journal
GPU-Accelerated Montgomery Exponentiation
ICCS '07 Proceedings of the 7th international conference on Computational Science, Part I: ICCS 2007
How to Maximize the Potential of FPGA Resources for Modular Exponentiation
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Simulations of modular multipliers on FPGA
AsiaMS '07 Proceedings of the IASTED Asian Conference on Modelling and Simulation
CT-RSA'08 Proceedings of the 2008 The Cryptopgraphers' Track at the RSA conference on Topics in cryptology
Design and implementation of real time secured RS232 link for multiple FPGA communication
Proceedings of the 2011 International Conference on Communication, Computing & Security
Revisiting sum of residues modular multiplication
Journal of Electrical and Computer Engineering
A fast RSA implementation on itanium 2 processor
ICICS'06 Proceedings of the 8th international conference on Information and Communications Security
Incorporating error detection in an RSA architecture
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
Exact analysis of montgomery multiplication
INDOCRYPT'04 Proceedings of the 5th international conference on Cryptology in India
Software implementation of modular exponentiation, using advanced vector instructions architectures
WAIFI'12 Proceedings of the 4th international conference on Arithmetic of Finite Fields
A compact FPGA-based montgomery multiplier over prime fields
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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Montgomery's modular multiplication algorithm has enabled considerable progress to be made in the speeding up of RSA cryptosystems. Perhaps the systolic array implementation stands out most in the history of its success. This article gives a brief history of its implementation in hardware, taking a broad view of the many aspects which need to be considered in chip design. Among these are trade-offs between area and time, higher radix methods, communications both within the circuitry and with the rest of the world, and, as the technology shrinks, testing, fault tolerance, checker functions and error correction. We conclude that a linear, pipelined implementation of the algorithm may be part of best policy in thwarting differential power attacks against RSA.