On the Time Required to Perform Addition
Journal of the ACM (JACM)
Journal of the ACM (JACM)
The Area-Time Complexity of Binary Multiplication
Journal of the ACM (JACM)
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Introduction to VLSI Systems
Structure of Computers and Computations
Structure of Computers and Computations
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
The chip complexity of binary arithmetic
STOC '80 Proceedings of the twelfth annual ACM symposium on Theory of computing
Area-efficient vlsi computation
Area-efficient vlsi computation
On the Addition of Binary Numbers
IEEE Transactions on Computers
A Survey of Some Recent Contributions to Computer Arithmetic
IEEE Transactions on Computers
A Heuristic for Suffix Solutions
IEEE Transactions on Computers
An Array Layout Methodology for VLSI Circuits
IEEE Transactions on Computers
IEEE Transactions on Computers
Optimal-time multipliers and C-testability
SPAA '90 Proceedings of the second annual ACM symposium on Parallel algorithms and architectures
Upper and lower bounds on switching energy in VLSI
Journal of the ACM (JACM)
Efficient Addition on Field Programmable Gate Arrays
FST TCS '01 Proceedings of the 21st Conference on Foundations of Software Technology and Theoretical Computer Science
Performance Comparison of VLSI Adders Using Logical Effort
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Montgomery's Multiplication Technique: How to Make It Smaller and Faster
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
High-Speed RSA Hardware Based on Barret's Modular Reduction Method
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Dynamic CMOS circuit techniques for delay and power reduction in parallel adders
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Micropipeline Architecture for Multiplier-less FIR Filters
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Delay-Insensitive Carry-Lookahead Adders
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders
IEEE Transactions on Computers
Faster optimal parallel prefix circuits: New algorithmic construction
Journal of Parallel and Distributed Computing
Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units
IEEE Transactions on Computers
Fast Modulo 2^{n} - (2^{n - 2} + 1) Addition: A New Class of Adder for RNS
IEEE Transactions on Computers
Fast Execution of Loops with IF Statements
IEEE Transactions on Computers
Timing-power optimization for mixed-radix ling adders by integer linear programming
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Variable latency speculative addition: a new paradigm for arithmetic circuit design
Proceedings of the conference on Design, automation and test in Europe
Straightforward construction of depth-size optimal, parallel prefix circuits with fan-out 2
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Parallel prefix algorithms on the multicomputer
WSEAS Transactions on Computer Research
Chai-Tea, Cryptographic Hardware Implementations of xTEA
INDOCRYPT '08 Proceedings of the 9th International Conference on Cryptology in India: Progress in Cryptology
Efficient modulo 2n+1 adder architectures
Integration, the VLSI Journal
Fast problem-size-independent parallel prefix circuits
Journal of Parallel and Distributed Computing
Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Evaluation of Sticky-Bit Generation Methods for Floating-Point Multipliers
Journal of Signal Processing Systems
A 485ps 64-bit parallel adder in 0.18µm CMOS
Journal of Computer Science and Technology
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
New parallel prefix algorithms
AIC'09 Proceedings of the 9th WSEAS international conference on Applied informatics and communications
A timing-driven hybrid-compression algorithm for faster Sum-of-Products
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
An area-time efficient NMOS adder
Integration, the VLSI Journal
New families of computation-efficient parallel prefix algorithms
WSEAS Transactions on Computers
FleXilicon architecture and its VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Constructive threshold logic addition: a synopsis of the last decade
ICANN/ICONIP'03 Proceedings of the 2003 joint international conference on Artificial neural networks and neural information processing
Design and implementation of a high-speed reconfigurable modular arithmetic unit
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
Constant addition with flagged binary adder architectures
Integration, the VLSI Journal
Improved area-efficient weighted modulo 2n+ 1 adder design with simple correction schemes
IEEE Transactions on Circuits and Systems II: Express Briefs
Time-to-digital converter for frequency synthesis based on a digital bang-bang DLL
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Functional and dynamic programming in the design of parallel prefix networks
Journal of Functional Programming
Power-delay characteristics of CMOS adders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Speculative carry generation with prefix adder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel hybrid parallel-prefix adder architecture with efficient timing-area characteristic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI micro-architectures for high-radix crossbar schedulers
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
A new optimized high-speed low-power data-driven dynamic (d3l) 32-bit kogge-stone adder
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Formal proof for a general architecture of hybrid prefix/carry-select adders
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Fast low-power 64-bit modular hybrid adder
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Wired: wire-aware circuit design
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
On teaching fast adder designs: revisiting ladner & fischer
Theoretical Computer Science
Mathematical and Computer Modelling: An International Journal
Energy-efficient single-clock-cycle binary comparator
International Journal of Circuit Theory and Applications
Fast parallel prefix logic circuits for n2n round-robin arbitration
Microelectronics Journal
Area-time efficient multi-modulus adders and their applications
Microprocessors & Microsystems
Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Area-time efficient end-around inverted carry adders
Integration, the VLSI Journal
Describing and optimising reversible logic using a functional language
IFL'11 Proceedings of the 23rd international conference on Implementation and Application of Functional Languages
Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures
Proceedings of the 50th Annual Design Automation Conference
Barrier invariants: a shared state abstraction for the analysis of data-dependent GPU kernels
Proceedings of the 2013 ACM SIGPLAN international conference on Object oriented programming systems languages & applications
A sound and complete abstraction for reasoning about parallel prefix sums
Proceedings of the 41st ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages
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With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.