Area-time efficient end-around inverted carry adders

  • Authors:
  • H. T. Vergos

  • Affiliations:
  • Computer Engineering & Informatics Department, University of Patras 26 500, Greece

  • Venue:
  • Integration, the VLSI Journal
  • Year:
  • 2012

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Abstract

Novel architectures for end-around inverted carry adders are proposed in this manuscript, which use a sparse carry computation unit for deriving only some of the carries in log"2n prefix levels, while all the rest are computed in an extra one. When used for the design of modulo 2^n+1 adders, the proposed designs offer significant area and power savings compared to earlier proposals, while maintaining a high operation speed.