Residue number system arithmetic: modern applications in digital signal processing
Residue number system arithmetic: modern applications in digital signal processing
A Simplified Architecture for Modulo (2n + 1) Multiplication
IEEE Transactions on Computers
Residue Number Systems: Algorithms and Architectures
Residue Number Systems: Algorithms and Architectures
Fast Combinatorial RNS Processors for DSP Applications
IEEE Transactions on Computers
Diminished-One Modulo 2^n +1 Adder Design
IEEE Transactions on Computers
U. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and Implementation
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Modulo 2n ± 1 Adder Design Using Select-Prefix Blocks
IEEE Transactions on Computers
High-Speed Parallel-Prefix VLSI Ling Adders
IEEE Transactions on Computers
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
Comment on the Sequential and Indeterminate Behavior of an End-Around-Carry Adder
IEEE Transactions on Computers
Residue Number Systems: Theory and Implementation
Residue Number Systems: Theory and Implementation
A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
IEEE Transactions on Computers
IBM Journal of Research and Development
Adaptive redundant residue number system coded multicarrier modulation
IEEE Journal on Selected Areas in Communications
Area-time efficient end-around inverted carry adders
Integration, the VLSI Journal
On the design of modulo 2n+1 dot product and generalized multiply-add units
Computers and Electrical Engineering
Efficient modulo 2n+1 multiplication for the idea block cipher
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Efficient modulo 2n+1 multiply and multiply-add units based on modified Booth encoding
Integration, the VLSI Journal
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In this manuscript, we introduce novel carry lookahead (CLA) and parallel-prefix architectures for the design of modulo 2^n+1 adders with operands in the diminished-1 number representation. The proposed architectures are based on the use of Ling carries' computation units and they lead to faster and/or smaller adders than the already known ones that are based on the traditional carry signals.