Residue number system arithmetic: modern applications in digital signal processing
Residue number system arithmetic: modern applications in digital signal processing
IEEE Transactions on Computers
Fast Base Extension Using a Redundant Modulus in RNS
IEEE Transactions on Computers
IEEE Transactions on Computers
A Spanning Tree Carry Lookahead Adder
IEEE Transactions on Computers - Special issue on computer arithmetic
'Overturned-Stairs' Adder Trees and Multiplier Design
IEEE Transactions on Computers - Special issue on computer arithmetic
A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation
IEEE Transactions on Computers - Special issue on computer arithmetic
Multirate Digital Signal Processing
Multirate Digital Signal Processing
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
Number Theory in Digital Signal Processing
Number Theory in Digital Signal Processing
A Single Chip Parallel Multiplier by MOS Technology
IEEE Transactions on Computers
Systolic Modular Multiplication
IEEE Transactions on Computers
A Systolic Redundant Residue Arithmetic Error Correction Circuit
IEEE Transactions on Computers
Large Dynamic Range Computations Over Small Finite Rings
IEEE Transactions on Computers
Computer
New Efficient Structure for a Modular Multiplier for RNS
IEEE Transactions on Computers
High-Speed and Reduced-Area Modular Adder Structures for RNS
IEEE Transactions on Computers
Journal of VLSI Signal Processing Systems
An RNS Architecture for Quasi-Chaotic Oscillators
Journal of VLSI Signal Processing Systems
Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies
Journal of VLSI Signal Processing Systems
Deterministic BIST for RNS Adders
IEEE Transactions on Computers
An arithmetic residue to binary conversion technique
Integration, the VLSI Journal
Fast Parallel-Prefix Modulo 2^n+1 Adders
IEEE Transactions on Computers
Efficient Diminished-1 Modulo 2^n+1 Multipliers
IEEE Transactions on Computers
Minimal energy asynchronous dynamic adders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient modulo 2n+1 adder architectures
Integration, the VLSI Journal
Fast scaling in the residue number system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast modulo 2n+1 multi-operand adders and residue generators
Integration, the VLSI Journal
A low-complexity high-radix RNS multiplier
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Hardware performance characterization of block cipher structures
CT-RSA'03 Proceedings of the 2003 RSA conference on The cryptographers' track
Parallel GF(3m) multiplier for trinomials
Information Processing Letters
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It is known that RNS VLSI processors can parallelize fixed-point addition and multiplication operations by the use of the Chinese Remainder Theorem (CRT). The required modular operations, however, must use specialized hardware whose design and implementation can create several problems. In this paper a modified residue arithmetic, called pseudo-RNS is introduced in order to alleviate some of the RNS problems when Digital Signal Processing (DSP) structures are implemented. Pseudo-RNS requires only the use of modified binary processors and exhibits a speed performance comparable with other RNS traditional approaches. Some applications of the pseudo-RNS to common DSP architectures, such as multipliers and filters, are also presented in this paper. They are compared in terms of the Area-Time Square product versus other RNS and weighted binary structures. It is proven that existing combinatorial or look-up table approaches for RNS are tailored to small designs or special applications, while the pseudo-RNS approach remains competitive also for complex systems.