Fast modulo 2n+1 multi-operand adders and residue generators

Authors:
H. T. Vergos;D. Bakalis;C. Efstathiou
Affiliations:
Computer Engineering and Informatics Department, University of Patras, 26500 Patras, Greece;Department of Physics, University of Patras, 26500 Patras, Greece;Informatics Department, ATEI of Athens, 12210 Athens, Greece
Venue:
Integration, the VLSI Journal
Year:
2010

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Abstract

In this manuscript novel architectures for modulo 2^n+1 multi-operand addition and residue generation are introduced. The proposed arithmetic components consist of a translation stage, an inverted end-around-carry carry-save-adder tree and an enhanced diminished-1 modulo 2^n+1 adder. Qualitative and quantitative results indicate that the proposed architectures result in significantly faster and in several cases smaller circuits than the previously proposed.