Residue number system arithmetic: modern applications in digital signal processing
Residue number system arithmetic: modern applications in digital signal processing
Residue arithmetic for a fault-tolerant multiplier: the choice of the best tripe of bases
Microprocessing and Microprogramming - Special issue short notes
Design and performance of the IBM Enterprise System/900 Type 9121 Vector Facility
IBM Journal of Research and Development
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
A New Approach to Fixed-Coefficient Inner Product Computation Over Finite Rings
IEEE Transactions on Computers
A CAD framework for generating self-checking multipliers based on residue codes
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes
Journal of Electronic Testing: Theory and Applications
High-Speed and Reduced-Area Modular Adder Structures for RNS
IEEE Transactions on Computers
Efficient Diminished-1 Modulo 2^n+1 Multipliers
IEEE Transactions on Computers
An efficient architecture for designing reverse converters based on a general three-moduli set
Journal of Systems Architecture: the EUROMICRO Journal
Self-Testing Embedded Borden t-UED Code Checkers for t=2kq-1 with q=2m-1
Journal of Electronic Testing: Theory and Applications
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Fast modulo 2n+1 multi-operand adders and residue generators
Integration, the VLSI Journal
International Journal of Critical Computer-Based Systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Fast and energy-efficient constant-coefficient FIR filters using residue number system
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Hierarchical residue number systems with small moduli and simple converters
International Journal of Applied Mathematics and Computer Science - Semantic Knowledge Engineering
CSD-RNS-based Single Constant Multipliers
Journal of Signal Processing Systems
Design of an RNS reverse converter for a new five-moduli special set
Proceedings of the great lakes symposium on VLSI
Design of the coarse-grained reconfigurable architecture DART with on-line error detection
Microprocessors & Microsystems
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Residue generator is an essential building block of encoding/decoding circuitry for arithmetic error detecting codes and binary-to-residue number system (RNS) converter. In either case, a residue generator is an overhead for a system and as such it should be built with minimum amount of hardware and should not compromise the speed of a system. Multioperand modular adder (MOMA) is a computational element used to implement various operations in digital signal processing systems using RNS. A comprehensive study of new residue generators and MOMA's is presented. The design methods given here take advantage of the periodicity of the series of powers of 2 taken module A (A is a module). Four design schemes of the n-input residue generators mod A, which are best suited for various pairs of n and A, are proposed. Their pipelined versions can be clocked with the cycle determined by the delay of a full-adder and a latch. A family of design methods for parallel and word-serial, using similar concepts, is also given. Both classes of circuits employ new highly-parallel schemes using carry-save adders with end-around carry and a minimal amount of ROM and are well-suited for VLSI implementation. They are faster and use less hardware than similar circuits known to date. One of the MOMA's can be used to build a high-speed residue-to-binary converter based on the Chinese remainder theorem.