Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes
IEEE Transactions on Computers
Computer arithmetic algorithms
Computer arithmetic algorithms
On-line testing for VLSI: state of the art and trends
Integration, the VLSI Journal - Special issue on VLSI testing
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Fault-Secure Parity Prediction Arithmetic Operators
IEEE Design & Test
Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders
IEEE Transactions on Computers
Proceedings of the IEEE International Test Conference
Design for soft-error robustness to rescue deep submicron scaling
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Carry checking/parity prediction adders and ALUs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Fault-secure shifter design: results and implementations
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Architecture Design for Soft Errors
Architecture Design for Soft Errors
Design of the coarse-grained reconfigurable architecture DART with on-line error detection
Microprocessors & Microsystems
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