ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
On-line testing for VLSI: state of the art and trends
Integration, the VLSI Journal - Special issue on VLSI testing
A CAD framework for generating self-checking multipliers based on residue codes
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Error Coding for Arithmetic Processors
Error Coding for Arithmetic Processors
Design for soft-error robustness to rescue deep submicron scaling
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Arithmetic Algorithms for Error-Coded Operands
IEEE Transactions on Computers
IBM Journal of Research and Development
Cost reduction and evaluation of temporary faults detecting technique
DATE '00 Proceedings of the conference on Design, automation and test in Europe
System safety through automatic high-level code transformations: an experimental evaluation
Proceedings of the conference on Design, automation and test in Europe
An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits
Journal of Electronic Testing: Theory and Applications
Online Testing Approach for Very Deep-Submicron ICs
IEEE Design & Test
Speeding-Up Fault Injection Campaigns in VHDL Models
SAFECOMP '00 Proceedings of the 19th International Conference on Computer Safety, Reliability and Security
REESE: A Method of Soft Error Detection in Microprocessors
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Concurrent Scan Monitoring and Multi-Pattern Search
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
New Techniques for Accelerating Fault Injection in VHDL Descriptions
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor
Journal of Electronic Testing: Theory and Applications
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A New Approach to Software-Implemented Fault Tolerance
Journal of Electronic Testing: Theory and Applications
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs
Journal of Electronic Testing: Theory and Applications
IC Cost Reduction by Applying Embedded Fault Tolerance for Soft Errors
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Reliable System Specification for Self-Checking Data-Paths
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits
Proceedings of the 42nd annual Design Automation Conference
A New Hybrid Fault Detection Technique for Systems-on-a-Chip
IEEE Transactions on Computers
Compiler-directed selective data protection against soft errors
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs
IEEE Transactions on Computers
Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Cost-efficient soft error protection for embedded microprocessors
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon
IEEE Design & Test
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs
Journal of Electronic Testing: Theory and Applications
Low-cost protection for SER upsets and silicon defects
Proceedings of the conference on Design, automation and test in Europe
A soft error robust and power aware memory design
Proceedings of the 20th annual conference on Integrated circuits and systems design
Majority Logic Mapping for Soft Error Dependability
Journal of Electronic Testing: Theory and Applications
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger
Journal of Electronic Testing: Theory and Applications
Soft error rate reduction using redundancy addition and removal
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Yield improvement and power aware low cost memory chips
Proceedings of the 2008 workshop on Radiation effects and fault tolerance in nanometer technologies
DVFS in loop accelerators using BLADES
Proceedings of the 45th annual Design Automation Conference
On the role of timing masking in reliable logic circuit design
Proceedings of the 45th annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
A delay-efficient radiation-hard digital design approach using CWSP elements
Proceedings of the conference on Design, automation and test in Europe
A case study in reliability-aware design: a resilient LDPC code decoder
Proceedings of the conference on Design, automation and test in Europe
Area Reliability Trade-Off in Improved Reed Muller Coding
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Power consumption of fault tolerant busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Efficient analytical determination of the SEU-induced pulse shape
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion
Journal of Electronic Testing: Theory and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Design of a soft-error robust microprocessor
Microelectronics Journal
Circuit techniques for dynamic variation tolerance
Proceedings of the 46th Annual Design Automation Conference
Improving testability and soft-error resilience through retiming
Proceedings of the 46th Annual Design Automation Conference
Checksum-based probabilistic transient-error compensation for linear digital systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Overscaling-friendly timing speculation architectures
Proceedings of the 20th symposium on Great lakes symposium on VLSI
False Error Vulnerability Study of On-line Soft Error Detection Mechanisms
Journal of Electronic Testing: Theory and Applications
Partitioning techniques for partially protected caches in resource-constrained embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Soft error modeling and remediation techniques in ASIC designs
Microelectronics Journal
A rapid prototyping system for error-resilient multi-processor systems-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
TIMBER: time borrowing and error relaying for online timing error resilience
Proceedings of the Conference on Design, Automation and Test in Europe
A unified online fault detection scheme via checking of stability violation
Proceedings of the Conference on Design, Automation and Test in Europe
Construction of SEU tolerant flip-flops allowing enhanced scan delay fault testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and optimization of nanometer CMOS circuits for soft-error tolerance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Re-synthesis for cost-efficient circuit-level timing speculation
Proceedings of the 48th Design Automation Conference
Inexact computing for ultra low-power nanometer digital circuit design
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Resilient microprocessor design for improving performance and energy efficiency
Proceedings of the International Conference on Computer-Aided Design
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Nanoscale technologies: prospect or hazard to dependable and secure computing?
LADC'07 Proceedings of the Third Latin-American conference on Dependable Computing
Case study on multiple fault dependability and security evaluations
Microprocessors & Microsystems
Correcting soft errors online in LU factorization
Proceedings of the 22nd international symposium on High-performance parallel and distributed computing
Reliability challenges of real-time systems in forthcoming technology nodes
Proceedings of the Conference on Design, Automation and Test in Europe
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection
Proceedings of the Conference on Design, Automation and Test in Europe
A low-cost, systematic methodology for soft error robustness of logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design for test and reliability in ultimate CMOS
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic
Journal of Electronic Testing: Theory and Applications
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
Effective Timing Error Tolerance in Flip-Flop Based Core Designs
Journal of Electronic Testing: Theory and Applications
Inexact computing using probabilistic circuits: Ultra low-power digital processing
ACM Journal on Emerging Technologies in Computing Systems (JETC)
On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
| Hi-index | 0.01 |
The increased operating frequencies, geometry shrinking and power supply reduction that accompany the process of very deep submicron scaling, affect the reliable operation of very deep submicron ICs. The effects of various noise sources are becoming of great concern. In particularly, it is predicted that single event upsets induced by alpha particles and cosmic radiation will become a cause of unacceptable error rates in future very deep submicron and nanometer technologies. This problem, concerning in the past more often parts used in space, will affect future ICs at sea level. This challenging problem has to be solved otherwise technological progress will be blocked soon. Thus, fault tolerant design is becoming necessary, even for commodity applications. But economic constraints of commodity applications exclude the use of traditional, high-cost fault tolerant techniques. This work uses time redundancy techniques to derive low cost soft-error tolerant implementations for logic networks.