Error-Checking Logic for Arithmetic-Type Operations of a Processor
IEEE Transactions on Computers
Arithmetic Error Codes: Cost and Effectiveness Studies for Application in Digital System Design
IEEE Transactions on Computers
AFIPS '65 (Fall, part I) Proceedings of the November 30--December 1, 1965, fall joint computer conference, part I
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Detection of Storage Errors in Mass Memories Using Low-Cost Arithmetic Error Codes
IEEE Transactions on Computers
An Algebraic Model of Fault-Masking Logic Circuits
IEEE Transactions on Computers
Data and computational fault detection mechanism for devices that perform modular exponentiation
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
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A set of arithmetic algorithms is described for operands that are encoded in the ``AN'' error-detecting code with the low-cost check modulus A = 2a - 1. The set includes addition additive inverse (complementation), multiplication, division, roundoff, and two auxiliary algorithms: ``multiply by 2a - 1,'' and ``divide by 2a - 1.'' The design of a serial radix-16 processor is presented in which these algorithms are implemented for the low-cost AN code with A = 15. This processor has been constructed for the Jet Propulsion Laboratory STAR computer. The adaptation of ``two's complement'' arithmetic for an inverse-residue code is also described.