Time redundant fault-location in bit-sliced ALU's
IEEE Transactions on Computers
Embedded self-testing checkers for low-cost arithmetic codes
ITC '98 Proceedings of the 1998 IEEE International Test Conference
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An On-Line Square Root Algorithm
IEEE Transactions on Computers
Detection of Unidirectional Multiple Errors Using Low-Cost Arithmetic Codes
IEEE Transactions on Computers
Error-Correcting Codes for Byte-Organized Arithmetic Processors
IEEE Transactions on Computers
Error-Correcting Codes in Binary-Coded Radix-r Arithmetic
IEEE Transactions on Computers
Comment on the Sequential and Indeterminate Behavior of an End-Around-Carry Adder
IEEE Transactions on Computers
Concurrent Error Detection in Multiply and Divide Arrays
IEEE Transactions on Computers
An Algebraic Model of Arithmetic Codes
IEEE Transactions on Computers
Detection of Storage Errors in Mass Memories Using Low-Cost Arithmetic Error Codes
IEEE Transactions on Computers
Modified Berger Codes for Detection of Unidirectional Errors
IEEE Transactions on Computers
Design and Application of Self-Testing Comparators Implemented with MOS PLA's
IEEE Transactions on Computers
Design of Self-Checking MOS-LSI Circuits: Application to a Four-Bit Microprocessor
IEEE Transactions on Computers
Concurrent Error Detection in ALU's by Recomputing with Shifted Operands
IEEE Transactions on Computers
On Totally Self-Checking Checkers for Separable Codes
IEEE Transactions on Computers
Reliability Analysis of Systems with Concurrent Error Detection
IEEE Transactions on Computers
Error-Correcting Codes in Binary-Coded-Decimal Arithmetic
IEEE Transactions on Computers
IEEE Transactions on Computers
Self-Testing Embedded Borden t-UED Code Checkers for t=2kq-1 with q=2m-1
Journal of Electronic Testing: Theory and Applications
Design of a fault-tolerant, modular computer with dynamic redundancy
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
An overview of fault-tolerant digital system architecture
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
Approaches to computer reliability: then and now
AFIPS '76 Proceedings of the June 7-10, 1976, national computer conference and exposition
Low-cost residue number systems for computer arithmetic
AFIPS '76 Proceedings of the June 7-10, 1976, national computer conference and exposition
Fault tolerance by means of external monitoring of computer systems
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
End-to-end register data-flow continuous self-test
Proceedings of the 36th annual international symposium on Computer architecture
AN-Encoding Compiler: Building Safety-Critical Systems with Commodity Hardware
SAFECOMP '09 Proceedings of the 28th International Conference on Computer Safety, Reliability, and Security
Arithmetic Algorithms for Error-Coded Operands
IEEE Transactions on Computers
Parallelizing Software-Implemented Error Detection
SEUS '09 Proceedings of the 7th IFIP WG 10.2 International Workshop on Software Technologies for Embedded and Ubiquitous Systems
Design techniques for cross-layer resilience
Proceedings of the Conference on Design, Automation and Test in Europe
ANB- and ANBDmem-encoding: detecting hardware errors in software
SAFECOMP'10 Proceedings of the 29th international conference on Computer safety, reliability, and security
HPCS'09 Proceedings of the 23rd international conference on High Performance Computing Systems and Applications
| Hi-index | 15.03 |
The application of error-detecting or error-correcting codes in digital computer design requires studies of cost and effectiveness trade-offs to supplement the knowledge of their theoretical properties. General criteria for cost and effectiveness studies of error codes are developed, and results are presented for arithmetic error codes with the low-cost check modulus 2a-1. Both separate