Introduction to VLSI Systems
Fault tolerance for vlsi multicomputers (self-checking, distributed-recovery, network)
Fault tolerance for vlsi multicomputers (self-checking, distributed-recovery, network)
Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes
IEEE Transactions on Computers
Efficient Design of Self-Checking Checker for any m-Out-of-n Code
IEEE Transactions on Computers
Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability
IEEE Transactions on Computers
Derivation and Calibration of a Transient Error Reliability Model
IEEE Transactions on Computers
Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's)
IEEE Transactions on Computers
Arithmetic Error Codes: Cost and Effectiveness Studies for Application in Digital System Design
IEEE Transactions on Computers
Computer
Optimum test patterns for parity networks
AFIPS '70 (Fall) Proceedings of the November 17-19, 1970, fall joint computer conference
Embedded self-testing checkers for low-cost arithmetic codes
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On CMOS totally self-checking circuits
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
A fault-tolerant permutation network modulo arithmetic processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A high probability of detecting errors caused by hardware faults is an essential property of any fault-tolerant system. VLSI technology makes the use of duplication and matching for error detection practical and attractive. A critical circuit in this context is a self-testing comparator. Faults in the comparator must be detected so that they do not mask discrepancies between the duplicated modules.