On fault detection in CMOS logic networks
DAC '83 Proceedings of the 20th Design Automation Conference
Test generation for MOS circuits using D-algorithm
DAC '83 Proceedings of the 20th Design Automation Conference
A gate level model for CMOS combinational logic circuits with application to fault detection
DAC '84 Proceedings of the 21st Design Automation Conference
Automatic test generation for stuck-open faults in CMOS VLSI
DAC '81 Proceedings of the 18th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
A New Design Method for m-Out-of-n TSC Checkers
IEEE Transactions on Computers
Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes
IEEE Transactions on Computers
PLA Implementation of k-out-of-n Code TSC Checker
IEEE Transactions on Computers
Design and Application of Self-Testing Comparators Implemented with MOS PLA's
IEEE Transactions on Computers
Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability
IEEE Transactions on Computers
Design of Self-Checking MOS-LSI Circuits: Application to a Four-Bit Microprocessor
IEEE Transactions on Computers
Procedures for Eliminating Static and Dynamic Hazards in Test Generation
IEEE Transactions on Computers
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To model faults in CMOS VLSI digital circuits, an augmented fault model comprising FET stuck-open and stuck-on faults, in addition to line stuck-at faults, is being used. Recently, it was discovered that delays in CMOS circuits under test. could invalidate tests derived by neglecting such delays. Thus, it is necessary to reinvestigate most of the existing design and test methods which are based on stuck-at fault models while considering CMOS digital circuits. One of the areas that requires such a revisit is that of self-checking circuits, due to the fact that the self-testing property of these circuits is dependent upon fault model adopted. In this paper, the problem of the design of CMOS totally self-checking checkers is considered when arbitrary delays in the circuit under test are allowed. Designs using both full CMOS and domino gates are considered. Several design procedures given earlier for totally self-checking checkers are analyzed under the augmented fault model. Adequate design rules are derived for some of the checkers, such that the self-testing property is retained for the augmented fault model.