A fault simulator for MOS LSI circuits
DAC '82 Proceedings of the 19th Design Automation Conference
Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits
IEEE Transactions on Computers
MOS test pattern generation using path algebras
IEEE Transactions on Computers
On accuracy of switch-level modeling of bridging faults in complex gates
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Multiple Stuck-Open Fault Detection in CMOS Logic Circuits
IEEE Transactions on Computers - Fault-Tolerant Computing
Test generation of stuck-open faults using stuck-at test sets in CMOS combinational circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
CMOS stuck-open fault detection using single test patterns
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A new approach to derive robust sets for stuck-open faults in CMOS combinational logic circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A method of delay fault test generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Journal of Electronic Testing: Theory and Applications
Transistor level test generation for MOS circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
SLS—a fast switch level simulator for verification and fault coverage analysis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Transistor-level test generation for physical failures in CMOS circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Mixed-level fault coverage estimation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Open Defects in CMOS RAM Address Decoders
IEEE Design & Test
Efficient Modular Design of TSC Checkers for M-out-of-2M-Codes
IEEE Transactions on Computers
IEEE Transactions on Computers
Test and Testability Techniques for Open Defects in RAM Address Decoders
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A gate level model for CMOS combinational logic circuits with application to fault detection
DAC '84 Proceedings of the 21st Design Automation Conference
EURO-DAC '90 Proceedings of the conference on European design automation
Fault modelling and fault equivalence in CMOS technology
EURO-DAC '90 Proceedings of the conference on European design automation
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Stuck-open and transition fault testing in CMOS complex gates
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Test generation for MOS circuits
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Built-in test for CMOS circuits
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
On CMOS totally self-checking circuits
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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An application of the D-algorithm in generating tests for MOS circuit faults is described. The MOS circuits considered are combinational and acyclic but may contain transmission gates and buses. Tests are generated for both, the stuck type faults and the transistor faults (open and short). A logic model is derived for the MOS circuits. In addition to the conventional logic gates, a new type of modeling block is used to represent the “memory” state caused by the “open” transistors. Every fault, whether a stuck type fault or a transistor fault, is represented in the model as a stuck fault at a certain gate input. For generating tests, however, the D-algorithm needs modification. The singular cover and the D-cubes for the new gate include some memory states. To handle the memory state, an initialization procedure has been added to the consistency part of the D-algorithm. The procedure of modeling and test generation is finally extended to transmission gates and buses.