On fault detection in CMOS logic networks
DAC '83 Proceedings of the 20th Design Automation Conference
Test generation for MOS circuits using D-algorithm
DAC '83 Proceedings of the 20th Design Automation Conference
Automatic test generation for stuck-open faults in CMOS VLSI
DAC '81 Proceedings of the 18th Design Automation Conference
Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
Fault-Tolerant Asynchronous Networks
IEEE Transactions on Computers
A rule-based circuit representation for automated CMOS design and verification
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Multiple Stuck-Open Fault Detection in CMOS Logic Circuits
IEEE Transactions on Computers - Fault-Tolerant Computing
CMOS stuck-open fault detection using single test patterns
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
On synthesizing and identifying stuck-open testable CMOS combinational circuits (extended abstract)
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays
IEEE Transactions on Computers
IEEE Transactions on Computers
ICPP '97 Proceedings of the international Conference on Parallel Processing
BIST design for detecting multiple stuck-open faults in CMOS circuits using transition count
Journal of Computer Science and Technology
New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
On Testability of Multiple Precharged Domino Logic
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
EURO-DAC '90 Proceedings of the conference on European design automation
Testable designs of multiple precharged domino circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 14.99 |
In this paper, potential invalidation of stuck-open fault-detecting tests, derived by neglecting circuit delays and charge distribution in CMOS logic circuits, is studied. Several classes of circuits derived from sum of products and product of sums expressions for a given combinational logic function are investigated to determine the testability of FET stuck-open faults by tests which will remain valid in the presence of arbitrary circuit delays. Necessary and sufficient conditions for the existence of tests that will remain valid in the presence of arbitrary circuit delays are derived. Using these conditions, it is shown that all single FET stuck-open faults, in a specific design using a single CMOs complex gate, are detectable by tests that remain valid in the presence of arbitrary circuit delays. For several other realizations, methods to augment them, to insure detectability of all single FET stuck-open faults by tests that will remain valid in the presence of arbitrary circuit delays are proposed. It is observed that in many of the logic circuits investigated it is also possible to avoid test invalidation due to charge distribution.