BIST design for detecting multiple stuck-open faults in CMOS circuits using transition count

Authors:
Hafizur Rahaman;Debesh K. Das;Bhargab B. Bhattacharya
Affiliations:
Indian Institute of Information Technology, Calcutta-700 106, India;Department of Computer Science and Engineering, Jadavpur University, Calcutta-700 032, India;ACM Unit, Indian Statistical Institute, Calcutta-700 108, India
Venue:
Journal of Computer Science and Technology
Year:
2002

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Abstract

This paper presents a built-in self-test (BIST) scheme for detecting all robustly testable multiple stuck-open faults confined to any single complex cell of a CMOS circuit. The test pattern generator (TPG) generates all n . 2n single-input-change (SIC) ordered test pairs for an n-input circuit-under-test (CUT) contained in a sequence of length 2n.2n. The proposed design is universal, i.e., independent of the structure and functionality of the CUT. A counter that counts the number of alternate transitions at the output of the CUT, is used as a signature analyzer (SA). The design of TPG and SA is simple and no special design- or synthesis-fortestability techniques and/or additional control lines are needed.