Spectral Techniques in Digital Logic
Spectral Techniques in Digital Logic
Testing by Verifying Walsh Coefficients
IEEE Transactions on Computers
Syndrome-Testable Design of Combinational Circuits
IEEE Transactions on Computers
A Practical Approach to Fault Detection in Combinational Networks
IEEE Transactions on Computers
Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks
IEEE Transactions on Computers
Multiple Fault Testing of Large Circuits by Single Fault Test Sets
IEEE Transactions on Computers
Spectral Fault Signatures for Internally Unate Combinational Networks
IEEE Transactions on Computers
A New Representation for Faults in Combinational Digital Circuits
IEEE Transactions on Computers
Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks
IEEE Transactions on Computers
Arithmetic Spectrum Applied to Fault Detection for Combinational Networks
IEEE Transactions on Computers
BIST design for detecting multiple stuck-open faults in CMOS circuits using transition count
Journal of Computer Science and Technology
| Hi-index | 14.98 |
Earlier spectral signature testing methods are extended to the multiple stuck-at fault model. The testability condition for multiple- input faults is established and a minimal spanning signature (MSS) is defined to cover all these faults. It is then shown that an MSS, which in most cases contains a single spectral coefficient, will detect over 99 percent of all input and internal multiple faults. An approach is described to obtain a complete signature for all multiple faults in any irredundant combinational network with comparatively small numbers of fan-outs. Tree networks that include XOR/XNOR gates are shown to be easily tested. Internally fan-out-free and general irredundant networks are also considered. A design approach is proposed to enable a network to be tested for all single and most multiple faults using a single coefficient, with the possible overhead being an extra control input.