Spectral Signature Testing of Multiple Stuck-at Faults in Irredundant Combinational Networks
IEEE Transactions on Computers
Testing programmable logic arrays by sum of syndromes
IEEE Transactions on Computers
Probabilistic Aspects of Boolean Switching Functions via a New Transform
Journal of the ACM (JACM)
Spectral Techniques in Digital Logic
Spectral Techniques in Digital Logic
Space compaction for multiple-output circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hyperneural Network-An Efficient Model for Test Generation in Digital Circuits
IEEE Transactions on Computers
A Note on the Polynomial Form of Boolean Functions and Related Topics
IEEE Transactions on Computers
Fast Linearly Independent Arithmetic Expansions
IEEE Transactions on Computers
A Unifying Approach to Edge-valued and Arithmetic Transform Decision Diagrams
Automation and Remote Control
Large Systems of Boolean Functions: Realization by Modular Arithmetic Methods
Automation and Remote Control
Automation and Remote Control
International Journal of Computer Mathematics
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A method for the derivation of fault signatures for the detection of faults in single-output combinational networks is described. The approach uses the arithmetic spectrum instead of the Rademacher-Walsh spectrum. It is a form of data compression that serves to reduce the volume of the response data at test time. The price which is paid for the reduction in the storage requirements is that some of the knowledge of exact fault location is lost. The derived signatures are short and easily tested using very simple test equipment. The test circuitry could be included on the chip since the overhead involved is comparatively small. The test procedure requires a high-speed counter cycling at maximum speed through selected subsets of all input combinations. Hence, the network under test is exercised at speed, and a number of dynamic errors that are not testable by means of conventional test-set approaches will be detected.