Computer - IEEE Centennial: the state of computing
Spectral Techniques in Digital Logic
Spectral Techniques in Digital Logic
Syndrome-Testable Design of Combinational Circuits
IEEE Transactions on Computers
Detection of Faults in Programmable Logic Arrays
IEEE Transactions on Computers
An Easily Testable Design of Programmable Logic Arrays for Multiple Faults
IEEE Transactions on Computers
The Weighted Syndrome Sums Approach to VLSI Testing
IEEE Transactions on Computers
Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks
IEEE Transactions on Computers
Arithmetic Spectrum Applied to Fault Detection for Combinational Networks
IEEE Transactions on Computers
Universal syndrome-testable design of programmable logic arrays
Integration, the VLSI Journal
| Hi-index | 14.98 |
Syndrome testing is a simple and effective fault detection technique applicable to many general circuits. It is particularly useful in two-level circuits, such as programmable logic arrays (PLA's). For a multiple-output network, like PLA's, existing methods test the individual syndromes for each function, where a fault should be detectable in at least one output. This paper shows that the weighted sum of syndromes of all the outputs covers all single stuck-at-faults, bridging faults, and cross-point faults. Primary input faults are also covered except in one special case which requires some preventive design for testability. This results in the use of one test to cover all single faults.