Detection of Faults in Programmable Logic Arrays

Authors:
J. E. Smith
Affiliations:
Department of Electrical and Computer Engineering, University of Wisconsin
Venue:
IEEE Transactions on Computers
Year:
1979

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Abstract

A new fault model is proposed for the purpose of testing programmable logic arrays. It is shown that a test set for all detectable modeled faults detects a wide variety of other faults. A test generation method for single faults is then outlined. Included is a bound on the size of test sets which indicates that test sets are much smaller than would be required by exhaustive testing. Finally, it is shown that many interesting classes of multiple faults are also detected by the test sets.