Introduction to VLSI Systems
Design for Testability A Survey
IEEE Transactions on Computers
Multiple Fault Detection in Programmable Logic Arrays
IEEE Transactions on Computers
A High Density Programmable Logic Array Chip
IEEE Transactions on Computers
Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's)
IEEE Transactions on Computers
Fault Detecting Test Sets for Reed-Muller Canonic Networks
IEEE Transactions on Computers
Detection of Faults in Programmable Logic Arrays
IEEE Transactions on Computers
A Design of Programmable Logic Arrays with Universal Tests
IEEE Transactions on Computers
Easily Testable Realizations ror Logic Functions
IEEE Transactions on Computers
An introduction to array logic
IBM Journal of Research and Development
Lower Overhead Design for Testability of Programmable Logic Arrays
IEEE Transactions on Computers - The MIT Press scientific computation series
A New Approach to the Design of Testable PLA's
IEEE Transactions on Computers
Testable PLA design with minimal overheads
Integration, the VLSI Journal
| Hi-index | 14.98 |
A new design of universally testable PLA's is presented in which all multiple faults can be detected by a universal test set which is independent of the function being realized by the PLA. The proposed design has the following properties. 1) It can be tested with function-independent test patterns; hence, no test pattern generation is required. 2) The amount of extra hardware is significantly decreased compared to the previous designs of universally testable PLA's. 3) Very high fault coverage is achieved, i. e., all single and multiple stuck faults, crosspoint faults, and adjacent line bridging faults are detected. 4) It is appropriate for built-in testing approaches. 5) It can be applied to the high-density PLA's using array folding techniques.