Minimization of Exclusive or and Logical Equivalence Switching Circuits
IEEE Transactions on Computers
Testing for faults in combinational cellular logic arrays
FOCS '67 Proceedings of the 8th Annual Symposium on Switching and Automata Theory (SWAT 1967)
Bridging Fault Detections for Testable Realizations of Logic Functions
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
IEEE Transactions on Computers
Design of Totally Fault Locatable Combinational Networks
IEEE Transactions on Computers
Design for Testability A Survey
IEEE Transactions on Computers
Unateness Properties of and-Exclusive-or Logic Circuits
IEEE Transactions on Computers
Universal Test Sets for Multiple Fault Detection in AND-EXOR Arrays
IEEE Transactions on Computers
Fault Diagnosis of MOS Combinational Networks
IEEE Transactions on Computers
Polynomially Complete Fault Detection Problems
IEEE Transactions on Computers
A Theory of Galois Switching Functions
IEEE Transactions on Computers
A Note on Easily Testable Realizations for Logic Functions
IEEE Transactions on Computers
Minimally Testable Reed-Muller Canonical Forms
IEEE Transactions on Computers
A Method for Modulo-2 Minimization
IEEE Transactions on Computers - Lecture notes in computer science Vol. 174
Fault Detecting Test Sets for Reed-Muller Canonic Networks
IEEE Transactions on Computers
Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results
IEEE Transactions on Computers
Synchronous Sequential Machines: A Modular and Testable Design
IEEE Transactions on Computers
Dual-Mode Logic for Function-Independent Fault Testing
IEEE Transactions on Computers
A Design of Programmable Logic Arrays with Universal Tests
IEEE Transactions on Computers
Complete Test Sets for Logic Functions
IEEE Transactions on Computers
Testable design of AND-EXOR logic networks with universal test sets
Computers and Electrical Engineering
Computers and Electrical Engineering
Exclusive-OR representations of Boolean functions
IBM Journal of Research and Development
A novel quantum genetic algorithm for area optimization of FPRM circuits
IITA'09 Proceedings of the 3rd international conference on Intelligent information technology application
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A New PLA Design for Universal Testability
IEEE Transactions on Computers
Diagnosis of faults in linear tree networks
IEEE Transactions on Computers
Hi-index | 15.03 |
Desirable properties of "easily testable networks" are given. A realization for arbitrary logic function, using AND and EXCLUSIVE-OR gates, based on Reed-Muller canonic expansion is given that has many of these desirable properties. If only permanent stuck-at-0 (s-a-0) or stuck-at-1 (s-a-1) faults occur in a single AND gate or only a single EXCLUSIVE-OR gate is faulty, the following results are derived on fault detecting test sets for the proposed networks: 1) only (n/4) tests, independent of the function being realized, are required if the primary inputs are fault-free; 2) only 2n, additional inputs (which depend on the function realized) are required if the primary inputs can be faulty, where n, is the number of variables appearing in even number of product terms in the Reed-Muller canonical expansion of the function; and 3) the additional 2ne inputs are not required if the network is provided with an observable point at the output of an extra AND gate.