Testability Conditions for Bilateral Arrays of Combinational Cells
IEEE Transactions on Computers
A minimum test set for multiple fault detection on ripple carry adders
IEEE Transactions on Computers
Robust Sequential Fault Testing of Iterative Logic Arrays
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Behavioral Fault Modeling in a VHDL Synthesis Environment
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Universal Test Generation Using Fault Tuples
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Effective BIST Scheme for Arithmetic Logic Un i t s
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Low Power BIST for Wallace Tree-Based Fast Multipliers
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Multiple-Fault Detection and Location in Fan-Out Free Combinational Circuits
IEEE Transactions on Computers
Fault Diagnosis and Repair of Cutpoint Cellular Arrays
IEEE Transactions on Computers
Tessellation Aspect of Combinational Cellular Array Testing
IEEE Transactions on Computers
Fault Detection in Iterative Logic Arrays
IEEE Transactions on Computers
An Approach to Highly Integrated, Computer-Maintained Cellular Arrays
IEEE Transactions on Computers
The Design of Easily Testable VLSI Array Multipliers
IEEE Transactions on Computers
Truth-Table Verification of an Iterative Logic Array
IEEE Transactions on Computers
Multiple Fault Detection in Arrays of Combinational Cells
IEEE Transactions on Computers
Cellular Logic-in-Memory Arrays
IEEE Transactions on Computers
Fault Detecting Test Sets for Reed-Muller Canonic Networks
IEEE Transactions on Computers
A Testable Design of Iterative Logic Arrays
IEEE Transactions on Computers
Design of Easily Testable Bit-Sliced Systems
IEEE Transactions on Computers
Design of Testable Structures Defined by Simple Loops
IEEE Transactions on Computers
Easily Testable Realizations ror Logic Functions
IEEE Transactions on Computers
Easily Testable Iterative Systems
IEEE Transactions on Computers
Self-Diagnosing Cellular Implementations of Finite-State Machines
IEEE Transactions on Computers
Fault Detection in Bilateral Arrays of Combinational Cells
IEEE Transactions on Computers
Testable Sequential Cellular Arrays
IEEE Transactions on Computers
Circuit Structure and Switching Function Verification
IEEE Transactions on Computers
IEEE Transactions on Computers
Recursive pseudo-exhaustive two-pattern generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fault Models for Quantum Mechanical Switching Networks
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computers
Design-for-testability and fault-tolerant techniques for FFT processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.07 |
Cellular logic arrays are beginning to take on an increasingly greater importance in digital technology, mainly because of their numerous advantages for the design, manufacture, and use in digital systems employing large-scale integrated semiconductor arrays. Particularly significant among these advantages is the feature of testability. One would naturally expect that the iterative structure and the short intercell connections of a cellular logic array would allow it to be tested from its edge terminals much more easily than a relatively disorganized interconnection of the same number of gates. In this paper we confirm this conjecture, and we describe procedures for deriving minimal (or near-minimal) schedules of test inputs, to be applied to a combinational cellular array in order to detect the presence of any single faulty cell. In addition, necessary and sufficient conditions are presented for some types of arrays of unilaterally connected, identical cells to be completely testable for single faults. For one-dimensional arrays, these conditions are based upon known results in sequential network theory. For two-dimensional arrays, a relationship to the "domino problem" (which is known to be insoluble) is described, but is shown to be largely avoidable and nonrestricting in the present case.