Journal of the ACM (JACM)
A Survey of Microcellular Research
Journal of the ACM (JACM)
Journal of the ACM (JACM)
A high-speed sorting procedure
Communications of the ACM
Fault Testing and Diagnosis in Combinational Digital Circuits
IEEE Transactions on Computers
Cellular Interconnection Arrays
IEEE Transactions on Computers
Associative self-sorting memory
IRE-AIEE-ACM '60 (Eastern) Papers presented at the December 13-15, 1960, eastern joint IRE-AIEE-ACM computer conference
AFIPS '65 (Fall, part I) Proceedings of the November 30--December 1, 1965, fall joint computer conference, part I
Sorting networks and their applications
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
Testing for faults in combinational cellular logic arrays
FOCS '67 Proceedings of the 8th Annual Symposium on Switching and Automata Theory (SWAT 1967)
A massively parallel implementation of the watershed based on cellular automata
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Two-Level Emitter-Function Logic Structures for Logic-in-Memory Computers
IEEE Transactions on Computers
Tessellation Aspect of Combinational Cellular Array Testing
IEEE Transactions on Computers
Programmable Array Realizations of Synchronous Sequential Machines
IEEE Transactions on Computers
A Design of a Fast Cellular Associative Memory for Ordered Retrieval
IEEE Transactions on Computers
A data sorting system using a high speed bus
AFIPS '75 Proceedings of the May 19-22, 1975, national computer conference and exposition
Interconnection networks: a survey and assessment
AFIPS '74 Proceedings of the May 6-10, 1974, national computer conference and exposition
IEEE Transactions on Computers
Testable Sequential Cellular Arrays
IEEE Transactions on Computers
MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Computers
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As a direct consequence of large-scale integration, many advantages in the design, fabrication, testing, and use of digital circuitry can be achieved if the circuits can be arranged in a two-dimensional iterative, or cellular, array of identical elementary networks, or cells. When a small amount of storage is included in each cell, the same array may be regarded either as a logically enhanced memory array, or as a logic array whose elementary gates and connections can be "programmed" to realize a desired logical behavior.