MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues

Authors:
Shoun Matsunaga;Jun Hayakawa;Shoji Ikeda;Katsuya Miura;Tetsuo Endoh;Hideo Ohno;Takahiro Hanyu
Affiliations:
Tohoku University, Sendai, Japan;Hitachi Advanced Research Laboratory, Tokyo, Japan;Tohoku University, Sendai, Japan;Hitachi Advanced Research Laboratory, Tokyo, Japan and Tohoku University, Sendai, Japan;Tohoku University, Sendai, Japan;Tohoku University, Sendai, Japan;Tohoku University, Sendai, Japan
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2009

Citing 2
Cited 1

TMR-Based Logic-in-Memory Circuit for Low-Power VLSI*

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Cellular Logic-in-Memory Arrays

IEEE Transactions on Computers

mLogic: ultra-low voltage non-volatile logic circuits using STT-MTJ devices

Proceedings of the 49th Annual Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. This paper presents novel nonvolatile logic circuits based on logic-in-memory architecture using magnetic tunnel junctions (MTJs) in combination with MOS transistors. Since the MTJ with a spin-injection write capability is only one device that has all the following superior features as large resistance ratio, virtually unlimited endurance, fast read/write accessibility, scalability, complementary MOS (CMOS)-process compatibility, and nonvolatility, it is very suited to implement the MOS/MTJ-hybrid logic circuit with logic-in-memory architecture. A concrete nonvolatile logic-in-memory circuit is designed and fabricated using a 0.18 μm CMOS/MTJ process, and its future prospects and issues are discussed.