Diagnostic Techniques for the IBM S/390 600 MHz G5 Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
IEEE Transactions on Computers
Generation of Optimal Transition Count Tests
IEEE Transactions on Computers
Application of Information Theory to Sequential Fault Diagnosis
IEEE Transactions on Computers
Multiple Fault Detection for Combinational Logic Circuits
IEEE Transactions on Computers
9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits
IEEE Transactions on Computers
Multiple Fault Detection in Combinational Circuits: Algorithms and Computational Results
IEEE Transactions on Computers
Sequential Fault Diagnosis in Combinational Networks
IEEE Transactions on Computers
A Module-Level Testing Approach for Combinational Networks
IEEE Transactions on Computers
Test Sets for Combinational Logic The Edge-Tracing Approach
IEEE Transactions on Computers
Cellular Logic-in-Memory Arrays
IEEE Transactions on Computers
System Modeling and Testing Procedures for Microdiagnostics
IEEE Transactions on Computers
An Analysis Model for Digital System Diagnosis
IEEE Transactions on Computers
Fault Diagnosis in Combinational Tree Networks
IEEE Transactions on Computers
A method of diagnostic test generation
AFIPS '69 (Spring) Proceedings of the May 14-16, 1969, spring joint computer conference
A method of test generation for fault location in combinational logic
AFIPS '70 (Fall) Proceedings of the November 17-19, 1970, fall joint computer conference
Functions for improving diagnostic resolution in an LSI environment
AFIPS '72 (Spring) Proceedings of the May 16-18, 1972, spring joint computer conference
Identification of Multiple Stuck-Type Faults in Combinational Networks
IEEE Transactions on Computers
S/390 G5 CMOS microprocessor diagnostics
IBM Journal of Research and Development
| Hi-index | 15.02 |
Abstract he problem of designing test schedules for the testing or diagnosis of a small number of nontransient faults in combinational digital circuits (switching networks) is considered in detail. By testing and diagnosis we mean the following: 1) detection of a fault, 2) location of a fault, and 3) location of a fault within the confines of a prescribed package or module. It is shown that minimal test schedules can be readily derived-using procedures already worked out for solving certain problems in pattern recognition and switching theory-under the assumption that the selection of the test inputs in the schedule is independent of the response of the circuit under test. When this assumption is not made, it is shown that much shorter test schedules are sometimes possible, and procedures are offered for obtaining good ones. Finally, the general status of diagnostics for digital circuits is reviewed and evaluated, and specific problems remaining to be solved are described.