Identification of Multiple Stuck-Type Faults in Combinational Networks

Authors:
Melvin A. Breuer;Shih-Jeh Chang;Stephen Y. H. Su
Affiliations:
Department of Electrical Engineering, University of Southern California, Los Angeles, CA 90007.;Department of Electrical Engineering, University of Southern California, Los Angeles, CA 90007./ Bell Telephone Laboratories, Columbus, OH 43213.;Department of Electrical Engineering, University of Southern California, Los Angeles, CA 90007./ Department of Electrical Engineering, Utah State University, Logan, UT 84322.
Venue:
IEEE Transactions on Computers
Year:
1976

Citing 12
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Multiple Fault Detection in Combinational Circuits: Algorithms and Computational Results

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A Nand Model ror Fault Diagnosis in Combinational Logic Networks

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Design of Totally Self-Checking Circuits with an Unrestricted Stuck-At Fault-Set Using Redundancy in Space and Time Domains

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Detection of Single, Stuck-Type Failures in Multivalued Combinational Networks

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Abstract

This paper deals with the problem of identifying multiple stuck-type hardware failures in combinational switching networks. Our work is an extension of that of Poage, and Bossen and Hong, and we employ the cause-effect equation for representing faulty circuit behavior. We introduce the concept of solving simultaneous equations over check point variables. These check point solutions are studied in detail. From the solutions one can calculate the function realized by a faulty circuit. We outline an on-line testing procedure for constructing a test set for identifying a specific fault in a circuit to within an equivalence class. This procedure eliminates the need for precalculating a fault dictionary, which, in many instances, can be quite advantageous. We also outline how to apply these techniques to the following problems: 1) identifying redundancy; 2) determining the set of faults not detected by an arbitrary test set; and 3) constructing a complete fault dictionary.