General Criterion for Essential Nonfault Locatability of Logical Functions
IEEE Transactions on Computers
Multiple-Fault Detection and Location in Fan-Out Free Combinational Circuits
IEEE Transactions on Computers
On Modifying Logic Networks to Improve Their Diagnosability
IEEE Transactions on Computers
Design of Totally Fault Locatable Combinational Networks
IEEE Transactions on Computers
Design for Testability A Survey
IEEE Transactions on Computers
A Tree Representation of Combinational Networks
IEEE Transactions on Computers
Multiple Fault Detection in Combinational Circuits: Algorithms and Computational Results
IEEE Transactions on Computers
Generic Fault Characterizations for Table Look-Up Coverage Bounding
IEEE Transactions on Computers
Fault Masking in Combinational Logic Circuits
IEEE Transactions on Computers
Optimal Detection of Bridge Faults and Stuck-At Faults in Two-Level Logic
IEEE Transactions on Computers
Transition Count Testing of Combinational Logic Circuits
IEEE Transactions on Computers
Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks
IEEE Transactions on Computers
Properties of Faults and Criticalities of Values under Tests for Combinational Networks
IEEE Transactions on Computers
On the Properties of Irredundant Logic Networks
IEEE Transactions on Computers
Multiple Fault Testing of Large Circuits by Single Fault Test Sets
IEEE Transactions on Computers
Resolution-Oriented Fault Interrelationships in Combinational Logic Networks
IEEE Transactions on Computers
Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect-Cause Analysis
IEEE Transactions on Computers
Fault Detection Capabilities of Alternating Logic
IEEE Transactions on Computers
Identification of Multiple Stuck-Type Faults in Combinational Networks
IEEE Transactions on Computers
A New Representation for Faults in Combinational Digital Circuits
IEEE Transactions on Computers
LSI logic testing: an overview
IEEE Transactions on Computers
| Hi-index | 15.04 |
A network model colled the normal NAND model is introduced for the study of fault diagnosis in combinational logic circuits. It is shown that every network can be transformed into an equivalent normal NAND network from which all the information pertaining to the diagnosis of the original network con be obtained. The use of this model greatly simplifies fault analysis and test generation.