Test Routines Based on Symbolic Logical Statements
Journal of the ACM (JACM)
The concurrent simulation of nearly identical digital networks
DAC '73 Proceedings of the 10th Design Automation Workshop
TEGAS2—anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic
DAC '72 Proceedings of the 9th Design Automation Workshop
Test generation systems in Japan
DAC '75 Proceedings of the 12th Design Automation Conference
A new look at test generation and verification
DAC '77 Proceedings of the 14th Design Automation Conference
A Design Verification and Logic Validation System
DAC '77 Proceedings of the 14th Design Automation Conference
PIRAMED project an integrated CAD/CAM system development
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Automatic checking of logic design structures For compliance with testability ground rules
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
IEEE Transactions on Computers
The Boolean Difference and Multiple Fault Analysis
IEEE Transactions on Computers
Comments on "Minimal Fault Tests for Combinational Networks"
IEEE Transactions on Computers
Boolean Differential Calculus and its Application to Switching Theory
IEEE Transactions on Computers
A Deductive Method for Simulating Faults in Logic Circuits
IEEE Transactions on Computers
Fault Masking in Combinational Logic Circuits
IEEE Transactions on Computers
A Heuristic Algorithm for the Testing of Asynchronous Circuits
IEEE Transactions on Computers
The Weighted Random Test-Pattern Generator
IEEE Transactions on Computers
Analyzing Errors with the Boolean Difference
IEEE Transactions on Computers
Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks
IEEE Transactions on Computers
Fault Equivalence in Combinational Logic Networks
IEEE Transactions on Computers
Comparison of Parallel and Deductive Fault Simulation Methods
IEEE Transactions on Computers
Fault Folding for Irredundant and Redundant Combinational Circuits
IEEE Transactions on Computers
Functional Partitioning and Simulation of Digital Circuits
IEEE Transactions on Computers
Modeling and Digital Simulation for Design Verification and Diagnosis
IEEE Transactions on Computers
A Nand Model ror Fault Diagnosis in Combinational Logic Networks
IEEE Transactions on Computers
Derivation of optimum test sequencies for sequential machines
SWCT '64 Proceedings of the 1964 Proceedings of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design
A model and implementation of a universal time delay simulator for large digital nets
AFIPS '70 (Spring) Proceedings of the May 5-7, 1970, spring joint computer conference
A New Representation for Faults in Combinational Digital Circuits
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
On the necessity to examine D-chains in diagnostic test generation-an example
IBM Journal of Research and Development
An integrated approach to automated computer maintenance
FOCS '65 Proceedings of the 6th Annual Symposium on Switching Circuit Theory and Logical Design (SWCT 1965)
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In this paper the development of large scale integration (LSI) testing is reviewed. The paper concentrates on the testing of logic components and presents in-depth discussions of the methods of fault modeling, test pattern generation, fault simulation, and design for testability. It is shown how these methods are used in the design of components and how they can be used in support of design automation. Finally, a brief account of test equipment and test data preparation is given.