A Design Verification and Logic Validation System

  • Authors:
  • William A. Noon

  • Affiliations:
  • -

  • Venue:
  • DAC '77 Proceedings of the 14th Design Automation Conference
  • Year:
  • 1977

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Abstract

This paper describes an experimental design specification language which is “engineer oriented” rather than “programmer oriented.” Computer programs using this language as input will Create a software model of the function description, statically and dynamically check for the completeness of the function described, check the logic implementation of the function for completeness and accuracy and generate a number of documents to provide clear communications.