DAC '81 Proceedings of the 18th Design Automation Conference
A set of programs for MOS design
DAC '81 Proceedings of the 18th Design Automation Conference
LSI components modelling in a three-valued functional simulation
DAC '78 Proceedings of the 15th Design Automation Conference
F/LOGIC - An interactive fault and logic simulator for digital circuits
DAC '76 Proceedings of the 13th Design Automation Conference
Detection of static and dynamic hazards in logic nets
DAC '77 Proceedings of the 14th Design Automation Conference
A Design Verification and Logic Validation System
DAC '77 Proceedings of the 14th Design Automation Conference
Digital logic simulation at the gate and functional level
DAC '79 Proceedings of the 16th Design Automation Conference
Formal Verification of Fault Tolerance Using Theorem-Proving Techniques
IEEE Transactions on Computers
Hardware logic simulation by compilation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A vertically integrated VLSI design environment
DAC '83 Proceedings of the 20th Design Automation Conference
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FML, a high-level function modelling language developed and used at Bell-Northern Research (BNR), is described in terms of its features, structure, timing capability and manner of execution. The language is presented, not in its full syntactic details, but by way of more helpful illustrations and examples. FML is fully integrated with BNR's functional simulator, FUNSIM, and thereby allows accurate timing and concurrent fault simulation. FML is a register level language with sub-register scheduling and tolerance timing, and it features an efficient mechanism for unknown state processing. To the user, FML is a circuit-designer-oriented, highly readable, easily applied design tool for both IC and PCB design.